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CODE CCE1010

 
TITLE Computer Logic 1

 
LEVEL 01 - Year 1 in Modular Undergraduate Course

 
ECTS CREDITS 6

 
DEPARTMENT Communications and Computer Engineering

 
DESCRIPTION The fundamental topics for combinational logic are studied in this unit. The unit also provides an understanding of computer number representations and basic arithmetic algorithms. These are developed to cover the design of a basic arithmetic unit using VHDL.

Study-unit Aims:

- To explain computer number representations and arithmetic algorithms.
- To explain the design of combinational logic systems.
- To explain the design of an ALU as used within a computer microprocessor.

Learning Outcomes:

1. Knowledge and understanding:

By the end of the study-unit the student will be able to:
- Understand the basic structure of the CPU with memory and peripherals.
- Understand logic gates, truth tables and Boolean algebra.
- Understand number representation and basic arithmetic: unsigned numbers, two’s complement, fixed-point and floating-point numbers, negation, addition and subtraction, shifting and rotation.
- Understand multiplexers and decoders.
- Understand technology parameters, including fan-in, fan-out, gate delays, glitches, tristate buffers, and power consumption.
- Understand the ALU as implemented using multiplexers and one full adder.
- Understand instruction sets: opcodes, operands and addressing modes.
- Understand multiplication algorithms including Booth’s algorithm.

2. Skills:

By the end of the study-unit the student will be able to:
- Implement combinational logic circuits using sum-of-product and product-of-sums techniques, and optimize using Karnaugh maps and the Quine-McCluskey method.
- Design adders and subtracters, with carry propagation and carry lookahead logic, and overflow detection.
- Implement combinational logic systems using VHDL.
- Simulate and validate combinational logic systems.
- Design, implement, simulate and validate an ALU.

Textbooks:

- D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd. ed., Morgan Kaufmann, 2013.
- W. Stallings, Computer Organization and Architecture, 9th. ed., Pearson, 2013.

 
ADDITIONAL NOTES Leads to: CCE1015, CCE2017

 
STUDY-UNIT TYPE Lecture and Tutorial

 
METHOD OF ASSESSMENT
Assessment Component/s Resit Availability Weighting
Practical No 20%
Examination (2 Hours) Yes 80%

 
LECTURER/S Trevor Spiteri (Co-ord.)

 
The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the study-unit description above applies to the academic year 2017/8, if study-unit is available during this academic year, and may be subject to change in subsequent years.
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The 13th Edition of EY’s Annual Attractiveness event will be held on 25th October 2017 at the InterContinental Hotel,

St. Julians. It is titled "Thinking without the box: disruption, technology and FDI".

 

The  students' invitation and more information can be found here

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