| CODE | CCE1013 | ||||||||||||||||||||
| TITLE | Computer Logic 1 | ||||||||||||||||||||
| UM LEVEL | 01 - Year 1 in Modular Undergraduate Course | ||||||||||||||||||||
| MQF LEVEL | 5 | ||||||||||||||||||||
| ECTS CREDITS | 5 | ||||||||||||||||||||
| DEPARTMENT | Communications and Computer Engineering | ||||||||||||||||||||
| DESCRIPTION | The fundamental topics for combinational logic are studied in this unit. The unit also provides an understanding of computer number representations and basic arithmetic algorithms. These are developed to cover the design of a basic arithmetic unit. Study-Unit Aims: - To explain computer number representations and arithmetic algorithms; - To explain the design of combinational logic systems; - To explain the design of an ALU as used within a computer microprocessor. Learning Outcomes: 1. Knowledge & Understanding: By the end of the study-unit the student will be able to: - describe logic gates, truth tables and Boolean algebra; - interpret number representation and perform basic arithmetic: unsigned numbers, two’s complement, fixed-point and floating-point numbers, negation, addition and subtraction, shifting and rotation, multiplication; - illustrate the use of multiplexers and decoders; - describe technology parameters, including fan-in, fan-out, delays, glitches, tristate buffers, and power consumption; - describe instruction sets; - distinguish between different addressing modes. 2. Skills: By the end of the study-unit the student will be able to: - implement combinational logic circuits using sum-of-product and product-of-sums techniques, and optimize using Karnaugh maps; - design adders and subtractors, with carry propagation and carry lookahead logic, and overflow detection; - implement combinational logic systems in hardware; - simulate and validate combinational logic systems; - design, implement, and validate an ALU using multiplexers and one full adder. Main Text/s and any supplementary readings: Main Texts: - D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd. ed., Morgan Kaufmann, 2013. - W. Stallings, Computer Organization and Architecture, 9th. ed., Pearson, 2013. |
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| STUDY-UNIT TYPE | Lecture and Tutorial | ||||||||||||||||||||
| METHOD OF ASSESSMENT |
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| LECTURER/S | Victor Buttigieg |
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The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints. Units not attracting a sufficient number of registrations may be withdrawn without notice. It should be noted that all the information in the description above applies to study-units available during the academic year 2023/4. It may be subject to change in subsequent years. |
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