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Study-Unit Description
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TITLE Digital VLSI Design

LEVEL 03 - Years 2, 3, 4 in Modular Undergraduate Course


DEPARTMENT Microelectronics and Nanoelectronics

DESCRIPTION The study-unit first covers principles and circuits of logic design in CMOS including timing and switching levels, gate circuits, ratioed and ratioless design, CMOS transmission gate, CMOS inverters, NOR and NAND logic circuits; comparison of switching times; buffer circuits; signal propagation delays, capacitive loading, power dissipation, noise in digital circuits.

The study-unit then looks at combinational logic implementation: random logic (inverter, NAND, NOR gates) CMOS implementation; transistor sizes and stick diagrams; structured combinational logic: transistor switch arrays, distributed gate arrays, programmable gate arrays.

The unit then moves on to the design of asynchronous sequential circuits: state diagrams and flow tables, internal state reduction, secondary state assignment; synchronisers: metastability, communicating between asynchronous clock domains, arbitrers, degrees of synchrony.

Finally the unit looks at testing and design for testability: fault matrix, path sensitisation, line justification, critical path generation; problems in testing and industrial test methods; scan path testing, built-in-self-test, BILBOs, use of controllability analysis.

Study-unit Aims

The study-unit aims at imparting to students the principles of digital logic design in integrated circuits, including random logic and structured logic implementation of combinational logic circuits.

In addition, the study unit aims at familiarising students with CAD tools required for the design of digital integrated circuits at semi-custom and full-custom level.

Learning Outcomes

1. Knowledge & Understanding: By the end of the study-unit the student will be able to:

- understand the principles entailed in digital logic integrated circuit ;
- determine test sequences to be used for verifying digital ICs.

2. Skills: By the end of the study-unit the student will be able to:

- design architectures with enhanced testability;
- design digital logic design in integrated circuits, will get familiar with CAD tools required for the design of integrated circuits at semi-custom and full-custom level and design testing structures for digital IC.

Main Text/s and any supplementary readings

- Geiger R., Allen P., Strader N., VLSI Design Techniques for Analog and Digital Circuits. McGraw-Hill, ISBN 0-07-100728-8. (Available at the Library)

Reading List:
- Fabricius E., Introduction to VLSI Design, McGraw-Hill, ISBN 0-07-100727-X. (Available at the Library)
- Lewis D. & Prothese D., Design of Logic Systems, Chapman & Hall, ISBN 0-412-42890-3. (Available at the Library)
- Pucknell D. & Eshraghian K., Basic VLSI Design, 3rd edition. Prentice Hall. ISBN 0-13-079153-9. (Available at the Library)

STUDY-UNIT TYPE Lecture, Practicum & Tutorial

Assessment Component/s Resit Availability Weighting
Practical No 20%
Examination (3 Hours) Yes 80%


The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the study-unit description above applies to the academic year 2017/8, if study-unit is available during this academic year, and may be subject to change in subsequent years.
Study-unit Registration Forms 2017/8


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