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Study-Unit Description
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TITLE Computer Logic 2

LEVEL 01 - Year 1 in Modular Undergraduate Course


DEPARTMENT Communications and Computer Engineering

DESCRIPTION The fundamental topics in sequential logic are covered in this unit. The topics include the ideas of state, and transitions between different states. The topic also demonstrates the use of sequential building blocks such as latches and flip-flops to design and implement systems such as shift registers and counters. These ideas are developed to include the design and implementation of finite state machines.

The unit also provides an understanding of sequential arithmetic algorithms used in computer design. The control unit is also explored, and the different implementation techniques are compared, with reference made to hardwired and microprogrammed control. Different memory technologies, such as SRAM and DRAM, are explored with attention to their different characteristics and their suitability for different applications.

Study-unit Aims:

- To explain the nature of state machines.
- To explain the design of sequential logic systems and state machines.
- To explain the design of a control unit as used within a computer microprocessor.

Learning Outcomes:

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to:
- Distinguish between sequential logic building blocks: RS latches, JK, D, T flip-flops.
- Interpret timing diagrams.
- Analyse and design shift registers and counters.
- Distinguish between Mealy and Moore FSMs.
- Illustrate sequential arithmetic algorithms, including floating-point arithmetic.
- Describe the instruction cycle and microoperations.
- Describe the buses and registers inside a computer microprocessor control unit.
- Distinguish between hardwired and microprogrammed control units.
- Contrast SRAM and DRAM.

2. Skills:

By the end of the study-unit the student will be able to:
- Implement sequential logic circuits using flip flops.
- Design finite state machines.
- Implement FSMs: excitation tables and state optimization, and VHDL implementation.
- Design a control unit using FSM techniques.
- Run a sequential logic system on an FPGA development board.

Main Text/s and any supplementary readings:

- D. M. Harris and S. L. Harris, Digital Design and Computer Architecture, 2nd. ed., Morgan Kaufmann, 2013.
- W. Stallings, Computer Organization and Architecture, 9th. ed., Pearson, 2013.


STUDY-UNIT TYPE Lecture, Independent Study, Practicum & Tutorial

Assessment Component/s Resit Availability Weighting
Practical No 20%
Examination (2 Hours) Yes 80%

LECTURER/S Trevor Spiteri

The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the study-unit description above applies to the academic year 2017/8, if study-unit is available during this academic year, and may be subject to change in subsequent years.
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