Study-Unit Description

Study-Unit Description


CODE MNE3502

 
TITLE Analogue VLSI 1

 
UM LEVEL 03 - Years 2, 3, 4 in Modular Undergraduate Course

 
MQF LEVEL 6

 
ECTS CREDITS 5

 
DEPARTMENT Microelectronics and Nanoelectronics

 
DESCRIPTION The study-unit covers the analysis and design of analogue integrated circuit building blocks and signal conditioning integrated circuits including current mirrors, differential amplifiers, single-stage and two-stage operational transconductance amplifiers, zero temperature coefficient voltage and current references, as well as introduces layout techniques used in analogue integrated-circuit design.

Study-unit Aims:

The study-unit aims at training students in the analysis and design of analogue IC building blocks and signal conditioning circuits including:
- current mirrors,
- differential amplifiers,
- single-stage and two-stage operational transconductance amplifiers,
- zero temperature coefficient voltage and current references.

The study-unit also aims at introducing students to layout techniques used in analogue integrated-circuit design.

Learning Outcomes:

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to:
- understand, analyse and design analogue building blocks and signal-conditioning circuits including current mirrors, single and two-stage OTAs, voltage and current references;
- appreciate issues in layout techniques used in analogue integrated-circuit design.

2. Skills:

By the end of the study-unit the student will be able to:
- carry out d.c. biasing analysis and a.c., small-signal, low-frequency and high-frequency analysis and design of analogue IC building blocks and signal-conditioning building blocks;
- use CADENCE framework software in connection with schematic capture design and simulation of advanced analogue signal-conditioning circuits;
- familiarise with layout techniques through CADENCE software.

Main Text/s and any supplementary readings:

- R.L. Geiger, P.E. Allen and N.R. Strader, "VLSI Design for Analog and Digital Circuits", McGraw-Hill, ISBN: 0-07-100728-8 (Available at Library)

 
STUDY-UNIT TYPE Lecture and Tutorial

 
METHOD OF ASSESSMENT
Assessment Component/s Assessment Due Sept. Asst Session Weighting
Assignment SEM1 Yes 25%
Examination (2 Hours) SEM1 Yes 75%

 
LECTURER/S Joseph Micallef (Co-ord.)

 

 
The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the description above applies to study-units available during the academic year 2023/4. It may be subject to change in subsequent years.

https://www.um.edu.mt/course/studyunit