https://www.um.edu.mt/library/oar/handle/123456789/2068 2026-04-09T14:48:01Z 2026-04-09T14:48:01Z https://www.um.edu.mt/library/oar/handle/123456789/145400 2026-04-08T07:53:05Z 2026-01-01T00:00:00Z

Title: Just-in-time framework for 8-bit systems Abstract: This project presents an emulator-integrated instrumentation framework designed to make runtime behaviour easier to observe during development and validation. The primary aim is to capture useful execution information with minimal disruption to normal emulation, allowing developers to inspect what the emulator is doing rather than relying on guesswork when behaviour differs from expectations. The framework is built around lightweight hooks that record instruction flow, memory access activity, and key events such as interrupts, and it exposes this information through a set of interactive tools including tracing, breakpoints, and memory activity visualisation. The framework is implemented as part of a complete emulator, using the Nintendo Entertainment System (NES) as a case study. The NES provides a well-documented and timing-sensitive platform where small behavioural differences are easy to trigger and useful to analyse. To evaluate the effectiveness of the design, the emulator was tested using established NES accuracy test ROM suites and results were compared against a reference emulator (Mesen). The evaluation focuses on whether the emulator reproduces expected behaviour on representative correctness and timing tests, and whether the integrated tooling provides practical value for fault isolation and behavioural inspection. While the project does not aim to replace mature emulators, it prioritises a clear architecture, extensible instrumentation, and practical usability, providing a solid foundation for further experimentation with correctness analysis and future optimisation work, such as performance profiling or dynamic binary translation. Description: B.Sc. (Hons)(Melit.)

2026-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/145399 2026-04-08T07:51:05Z 2026-01-01T00:00:00Z

Title: Accelerating diffuse indirect lighting with irradiance caching Abstract: Diffuse indirect lighting is a subset of global illumination that can be quite computationally expensive to compute. While Path Tracing is the standard for computing it, several techniques have been proposed to accelerate its computation, one of which being Irradiance Caching. In order to investigate whether the gain in performance by the irradiance cache is feasible in terms of change in quality, a multithreaded C++ implementation was developed and integrated into a custom hybrid Path-Tracing and Distributed Ray-tracing solution. The solution was evaluated using a set of test scenes and a number of sample counts, of which the results were compared to that of a reference path tracer. The two solutions are compared based on performance metrics such as render time, and quality metrics such as SSIM and PSNR. Based on the results obtained, it was concluded that the solution offers a significant gain in performance, and is deemed appropriate to replace path tracing in cases where accuracy is not the top priority. However, when accuracy and unbiased rendering are the top priority, the more traditional method of path tracing would be more suitable. Description: B.Sc. (Hons)(Melit.)

2026-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/145391 2026-04-08T06:15:49Z 2026-01-01T00:00:00Z

Title: Radio system architecture for a UHF frequency-multiplexed phased-array pico-satellite ground station Abstract: Recent years have seen a surge in low-Earth-orbit (LEO) small-satellite activity along with a corresponding demand for agile, low-cost ground stations (GSs). Building on this momentum, the University of Malta’s (UM) satellite efforts through the Astrionics Research Group’s ASTREA project aim to conduct in-orbit validation, including testing of materials and electronic components. Drawing on these efforts, this dissertation surveys a frequency-multiplexed phased-array (FMPA) GS for ultra-high-frequency (UHF) P-band satellite links, targeting affordability by using commercial off-the-shelf (COTS) components. To date, more than one thousand five hundred nano-satellites operate in the UHF band, remaining the most utilised choice for launched operations. Presently, the GS configuration requires sixty-four coaxial cable runs beneath the icosahedral geodesic-dome phased-array antenna (GDPAA). Frequency-division multiplexing (FDM) in the FMPA architecture collapses these to two, enabling a compact GS stack with a full complement of usable antenna elements (AEs) and reduced maintenance effort. This study frames and evaluates five candidate architectures, then shortlists two that apply AE-level phasing for beamforming and beam steering, either in software or hardware, culminating in a system (HardwarePS1) enabling multibeam, bidirectional operation. At the target 435 MHz, results confirm feasibility by exceeding ASTREA mission requirements, with the uplink budget yielding a 14.2 dB margin using two GDPAA planar faces, and the downlink achieves −124.9 dBm noise floor through a cascaded noise figure (NF) equivalent to approximately 576 K system noise temperature, delivering a 6.2 dB link margin. End-to-end MATLAB Simulink RF Blockset simulations, including device nonidealities across both signal chains and a 290 K thermal white-noise model, corroborate the operating point to nearly −59 dBc at the desired frequency. From a cost perspective, the baseline bill of materials (BoM) costs roughly €10,500, excluding printed circuit board (PCB) fabrication, while still maintaining the low-cost objective relative to phased-array alternatives. Finally, this work proposes the first reported FMPA uplink and end-to-end UHF operation with hardware-based phasing, indicating a credible, scalable path to multi-satellite GS operations aligned with contemporary LEO mission payloads. Description: M.Sc.(Melit.)

2026-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/145390 2026-04-08T06:13:50Z 2026-01-01T00:00:00Z

Title: Sequential decoding of convolutional codes under insertion and deletion errors Abstract: Synchronisation errors pose a major challenge to classical error-correcting decoding algorithms, which typically assume perfect alignment between transmitted and received sequences. Such errors arise in modern communication and storage systems, including packet-based networks and DNA-based storage where maintaining symbol synchronisation cannot be guaranteed. This dissertation addresses this challenge by implementing a Stack sequential decoder tailored for the Binary Substitution, Insertion and Deletion (BSID) channel and by integrating it as a new module within the SimCommSys simulation framework. The decoder works with convolutional codes and incorporates three path-metric formulations drawn from literature: a joint-distribution based metric; a conditional probability based metric and a weighted Levenshtein distance (WLD) based metric, allowing a unified comparison of their performance under synchronisation errors. Simulation results confirm that the implemented decoder operates correctly across a wide range of error conditions and convolutional codes. The implementation matches or closely replicates reference results from literature, validating the correctness of the metrics and the decoding logic. Among the three metrics, the joint-distribution based metric demonstrated the most robust overall performance after a detailed comparison of decoding performance and complexity with different convolutional codes. Overall, this work provides both a practical contribution with a fully functional sequential decoder for synchronisation errors and a comparative study that clarifies the strengths of three different metric formulations. The decoder serves as a foundation for future developments and research in sequential decoding under synchronisation errors. Description: M.Sc.(Melit.)

2026-01-01T00:00:00Z