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  <title>OAR@UM Collection:</title>
  <link rel="alternate" href="https://www.um.edu.mt/library/oar/handle/123456789/77598" />
  <subtitle />
  <id>https://www.um.edu.mt/library/oar/handle/123456789/77598</id>
  <updated>2026-04-16T06:42:35Z</updated>
  <dc:date>2026-04-16T06:42:35Z</dc:date>
  <entry>
    <title>Using an RTOS to control digital boards in SKA</title>
    <link rel="alternate" href="https://www.um.edu.mt/library/oar/handle/123456789/77615" />
    <author>
      <name />
    </author>
    <id>https://www.um.edu.mt/library/oar/handle/123456789/77615</id>
    <updated>2021-06-24T06:13:08Z</updated>
    <published>2016-01-01T00:00:00Z</published>
    <summary type="text">Title: Using an RTOS to control digital boards in SKA
Abstract: The Square Kilometre Array will be the largest radio telescope ever built. The prototype &#xD;
developed as part of this dissertation can form part of the monitoring and control system &#xD;
of the SKA project. &#xD;
The prototype will run on an ARM Cortex-M4 processor on the Tile Processing Modules &#xD;
(TPMs). The main functions of the prototype software will be to monitor and control the &#xD;
on-board Field Programmable Gate Arrays (FPGAs), upgrade their firmware and connect &#xD;
the TPM boards to the overall monitoring system. The monitoring and control system is &#xD;
made up of different components including the Telescope Manager (TM), the Monitoring &#xD;
Control and Calibration Servers (MCCS) and the TPMs themselves. These all need to &#xD;
communicate with each other to maintain a heterogeneous ecosystem. &#xD;
A Real-time Operating System (RTOS) running a custom application developed as part of &#xD;
this dissertation runs on the processor. Using an RTOS allows the developed pipeline to be &#xD;
easily ported to different micro-processor architectures with no changes to the pipeline &#xD;
itself. This is achieved through the layers of abstraction provided by the RTOS. The &#xD;
monitoring components in turn communicate with a Complex Programmable Logic Device &#xD;
(CPLD) present on the TPMs through the developed framework. The FPGA registers and &#xD;
memory regions are memory mapped to the CPLD's memory space. This mapping allows &#xD;
the CPLD to control the boards through its firmware. &#xD;
This project also investigates the functional requirements of the RTOS and the developed &#xD;
application. During this dissertation the software architecture that allows the interactions &#xD;
between the processor and the DSP was designed. A working prototype on which &#xD;
evaluation tests were performed was implemented. The platform proved to provide a fast &#xD;
reliable means of interaction over the user datagram protocol (UDP) and all the tests &#xD;
performed resulted in positive results.
Description: M.SC.ASTROINFORMATICS</summary>
    <dc:date>2016-01-01T00:00:00Z</dc:date>
  </entry>
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