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    <title>OAR@UM Collection:</title>
    <link>https://www.um.edu.mt/library/oar/handle/123456789/14669</link>
    <description />
    <pubDate>Tue, 28 Apr 2026 04:03:21 GMT</pubDate>
    <dc:date>2026-04-28T04:03:21Z</dc:date>
    <item>
      <title>High performance CMOS frequency synthesis architectures for microwave applications</title>
      <link>https://www.um.edu.mt/library/oar/handle/123456789/101436</link>
      <description>Title: High performance CMOS frequency synthesis architectures for microwave applications
Abstract: The motivation of this research was to investigate novel low voltage microwave &#xD;
frequency synthesizer architectures which can provide a wide range of frequencies &#xD;
with an acceptable phase noise response, integrated spurious level and power &#xD;
consumption as required by modem communication systems. In particular the work &#xD;
undertaken and described in this dissertation can be classified into three main parts. &#xD;
The first part reports the study, design and silicon implementation of a low voltage &#xD;
1.6 GHz quadrature output integer-N phase locked loop based frequency synthesizer &#xD;
with an on-chip regulated DC-DC converter in order to achieve a wide tuning range &#xD;
with negligible effect on the phase noise and spurious level. &#xD;
The second part discusses the investigation of the use of a Micro-electro-mechanical &#xD;
Systems (MEMS) based tuneable inductor both as a means to extend the frequency &#xD;
tuning range and also to facilitate and improve the voltage-controlled oscillator &#xD;
design in terms of phase noise response and power consumption in comparison to a &#xD;
design based on conventional capacitive tuning. &#xD;
Finally, the last part of the dissertation discusses the investigation of the spurious &#xD;
tone levels in novel digitally based frequency synthesis architectures for an Ultra &#xD;
Wideband MB-OFDM (Multi-band Orthogonal Frequency Division Multiplexing) &#xD;
Alliance application which requires a wide range of frequencies. Architectures are &#xD;
proposed as low silicon area alternatives to state-of-the-art solutions.
Description: PH.D.</description>
      <pubDate>Fri, 01 Jan 2010 00:00:00 GMT</pubDate>
      <guid isPermaLink="false">https://www.um.edu.mt/library/oar/handle/123456789/101436</guid>
      <dc:date>2010-01-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>A generic generic algorithm using phenotype building functions</title>
      <link>https://www.um.edu.mt/library/oar/handle/123456789/95821</link>
      <description>Title: A generic generic algorithm using phenotype building functions
Abstract: The problem with genetic algorithms is that their use is made difficult by the fact that they are not very&#xD;
reusable because the chromosome representation, genetic operators and fitness function need to be&#xD;
redefined for many problems. In order to use a genetic algorithm you have to think in terms of evolution&#xD;
which might not be easy for a programmer. In this project, we aim to solve these problems by creating a&#xD;
generic chromosome representation which always uses the same genetic algorithm regardless of the&#xD;
problem being solved. The user then directs the genetic algorithm by writing a function, called the&#xD;
'phenotype building function' or the 'builder function', which maps the generic chromosome into&#xD;
candidate solutions. The fitness function will still have to be provided in order to measure the fitness of&#xD;
a candidate solution.
Description: B.Sc. IT (Hons)(Melit.)</description>
      <pubDate>Fri, 01 Jan 2010 00:00:00 GMT</pubDate>
      <guid isPermaLink="false">https://www.um.edu.mt/library/oar/handle/123456789/95821</guid>
      <dc:date>2010-01-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Aircraft autoland system using fuzzy logic</title>
      <link>https://www.um.edu.mt/library/oar/handle/123456789/95804</link>
      <description>Title: Aircraft autoland system using fuzzy logic
Abstract: A full aircraft Autoland system using fuzzy logic has been developed. It is based on the&#xD;
flight model of a medium sized commercial airliner (Boeing 73 7-800), and was designed&#xD;
for a full 6 degree of freedom flight simulator. This was achieved by implementing&#xD;
several independent single output Fuzzy Controllers that are able to work together&#xD;
based on instrument readings continuously taken from the aircraft. Scenarios the&#xD;
solution was tested in include varying glidepath angles, various weather situations that&#xD;
include severe stable crosswinds and severe gusting crosswinds. For each case, the final&#xD;
results show that not only were safe landings performed in cases where the conditions&#xD;
were within the limitations set by the aircraft's manufacturer but also in worse&#xD;
conditions. These include landing in airports with a steep glidepath angle (such as&#xD;
London City Airport) but also landing in extreme crosswind conditions nearly double&#xD;
that of what the manufacturers recommend is used as a limitation.
Description: B.Sc. IT (Hons)(Melit.)</description>
      <pubDate>Fri, 01 Jan 2010 00:00:00 GMT</pubDate>
      <guid isPermaLink="false">https://www.um.edu.mt/library/oar/handle/123456789/95804</guid>
      <dc:date>2010-01-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Implementation of a baseband GPS receiver</title>
      <link>https://www.um.edu.mt/library/oar/handle/123456789/95632</link>
      <description>Title: Implementation of a baseband GPS receiver
Abstract: The Global Positioning System (GPS) is a space-based radio navigation system which&#xD;
was originally developed for military use. However, GPS receivers have become more&#xD;
popular in recent years and are now incorporated in mobile phone electronics and also&#xD;
in navigation systems, namely in automotive, marine and aerospace equipment.&#xD;
This thesis focuses on digital signal processing (DSP) performed by a typical L 1-hand&#xD;
Cl A-code receiver. Such baseband processing mainly involves local carrier and&#xD;
pseudo-random noise (PRN) code generation, converting the incoming GPS signal&#xD;
down to baseband, correlating the resulting baseband signal with the locally generated&#xD;
codes, determining the available satellites and subsequently choosing at least four of&#xD;
them, phase-aligning the local and incoming codes of the selected satellites, and finally,&#xD;
detecting and demodulating the navigation messages from the individual selected&#xD;
satellites. Thus, this dissertation presents the design and implementation of various&#xD;
DSP and communication blocks which are responsible for such baseband processing.&#xD;
In this work, perfect carrier phase recovery is assumed. These baseband digital&#xD;
modules are implemented on an FPGA. Such approach allows additional flexibility in&#xD;
the implementation when compared to the ASIC approach, due to the chip's reprogrammability feature. The functionality of each module is tested and verified.&#xD;
A GPS satellite signal modulation model is also developed to test and simulate the&#xD;
baseband processor for different scenarios, for example for multiple satellite&#xD;
transmissions and in the presence of noise. From these tests, it is noted that as the&#xD;
number of parallel transmissions is increased or when the SNR is decreased, the&#xD;
correlation between the incoming and local codes of the visible satellites is reduced.&#xD;
The minimum SNR value that the designed baseband processor can tolerate is -10 dB.&#xD;
For SNR values greater than or equal to this value, it is guaranteed that navigation&#xD;
messages from the different selected satellites are decoded correctly. This only holds if&#xD;
automatic gain control is adopted. If no gain control is used, the minimum SNR value&#xD;
that the processor can tolerate is greater than -10 dB. Good noise performance is&#xD;
crucial in GPS receivers since, in practice, the noise power level is significantly greater&#xD;
than the actual GPS signal power level.
Description: B.SC.(HONS)COMPUTER ENG.</description>
      <pubDate>Fri, 01 Jan 2010 00:00:00 GMT</pubDate>
      <guid isPermaLink="false">https://www.um.edu.mt/library/oar/handle/123456789/95632</guid>
      <dc:date>2010-01-01T00:00:00Z</dc:date>
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