https://www.um.edu.mt/library/oar/handle/123456789/27854 Sun, 24 May 2026 19:28:31 GMT 2026-05-24T19:28:31Z https://www.um.edu.mt/library/oar/handle/123456789/28185 Title: Seamless parallel computing on heterogeneous networks of multiprocessor workstations Authors: Vella, Kevin Abstract: This thesis is concerned with portable, efficient, and, above all, seamless parallel programming of heterogeneous networks of shared memory multiprocessor workstations. The CSP model of concurrency as embodied in the occam language is used to purvey an architecture-independent and elegant view of concurrent systems. Tools and techniques for efficiently executing finely decomposed parallel programs on uniprocessor workstations, shared memory multiprocessor workstations and networks of both are examined in some detail. In particular, scheduling strategies that batch related processes together to reduce cache-related context switching overheads on uniprocessors, and to reduce contention and false sharing on shared memory multiprocessors are studied. New wait-free CP channel algorithms for shared memory multiprocessors are presented, as well as implementations of CSP channel algorithms across commodity network interconnects. A virtual parallel computer abstraction is applied to hide the inherent heterogeneity of workstation networks and enable seamless execution of parallel programs. An investigation of the performance of moderate to very fine grain parallelism on uniprocessors and shared memory multiprocessors is presented. The performance of CSP channels across TCP/IP networks is also scrutinized. The results indicate that fine grain parallelism can be handled efficiently in software on uniprocessors and shared memory multiprocessors, though issues related to caching warrant careful consideration. Other results also show that a limited amount of computation-communication overlap can be attained even with commodity network adapters which require significant processor interaction to sustain data transfer. This thesis demonstrates that seamless parallel programming across a variety of contemporary architectures using the CSP/occam model is a viable, as well as an attractive, option. Tue, 01 Dec 1998 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/28185 1998-12-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/27858 Title: Hardware design based on Verilog HDL Abstract: Up to a few years ago, the approaches taken to check whether a hardware com- ponent works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empiri- cally) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a unified approach to hardware design in which both simulation and formal verification can co-exist. Relational Duration Calculus (an extension of Duration Calculus) is devel- oped and used to define the formal semantics of Verilog HDL (a standard indus- try hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hard- ware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog pro- grams, formal verification and the use of algebraic laws during the design stage. A simple operational semantics based on the simulation cycle is shown to be isomorphic to the denotational semantics. A number of laws which programs satisfy are also given, and can be used for the comparison of syntactically dif- ferent programs. The thesis also presents a number of other results. The use of a temporal logic to specify the semantics of the language makes the development of pro- grams which satisfy real-time properties relatively easy. This is shown in a case study. The fuzzy boundary in interpreting Verilog programs as either hardware or software is also exploited by developing a compilation procedure to translate programs into hardware. Hence, the two extreme interpretations of hardware description languages as software, with sequential composition as the topmost operator (as in simulation), and as hardware with parallel composition as the topmost operator are exposed. The results achieved are not limited to Verilog. The approach taken was carefully chosen so as to be applicable to other standard hardware description languages such as VHDL. Thu, 01 Jan 1998 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/27858 1998-01-01T00:00:00Z