https://www.um.edu.mt/library/oar/handle/123456789/53951 Sun, 12 Apr 2026 10:33:15 GMT 2026-04-12T10:33:15Z https://www.um.edu.mt/library/oar/handle/123456789/73723 Title: Modelling, characterisation and design optimisation of an ironless inductive position sensor Abstract: Safety critical systems such as particle accelerators and nuclear plants strongly depend on the sensors that control the system. The Large Hadron Collider (LHC) found at the European Organisation for Nuclear Research (CERN) depends on a collimation system to control the beam. The jaw position with respect to the beam of particles is measured with linear position sensors. The traditional transducer used for this task is the Linear Variable Differential Transformer (LVDT) while a newer transducer called the Ironless Inductive Position Sensor (I2PS) is taking up the LVDT’s place, in areas characterised with magnetic interference. An electrical metrological characterisation of the transducer, with long cables, is first presented. The frequency response of the sensor is conducted to assess the I2PS sensitivity at different frequencies with different cable lengths. Moreover, a set of experimental results are performed to assess the I2PS’s sensitivity to cable capacitance change. Comparison with a commercial off-the-shelf LVDT is presented, knowing that this was required to gain a better understanding. A novel SPICE simulation that models the I2PS sensor and its electronics is consequently developed. Furthermore, a countermeasure circuit is presented to eliminate the effects of cable capacitance. A detailed thermal analysis is then presented which characterises the impact of ambient temperature change on the sensor. This study itself becomes an important step in developing changes and defining guidelines, which optimise the stability of the I2PS. A number of modifications to the sensor are proposed to reduce the drift, making the sensor more robust. Nevertheless, not all solutions lead to sensor immunisation, given the unavoidable design of the transducer. Furthermore, a detailed study of operating multiple I2PS in close proximity at the same frequency is presented. Finally, this work also identifies the optimisation parameters and constants required when manually designing an I2PS. Consequently, it presents an automated design procedure, which when powered by a multi-objective optimisation algorithm, it automatically produces an I2PS, tailor made to the user’s specifications, very quickly by a user with minimal training. The research provided in this thesis presents a more thorough characterisation of the thermal and electrical behaviour of the transducer. This is accomplished by taking into consideration typical and infrequent circumstances of the operation of the LHC collimator system. Description: PH.D. Tue, 01 Jan 2019 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/73723 2019-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/55233 Title: HF digital radio Abstract: Communications has and most likely will always be among the most important cornerstones supporting human enterprise and innovation. Among the more niche yet fundamental methods of communication is that provided via High Frequency (HF) radio. With the use of a dedicated radio transceiver and antenna, communication is made available to others almost literally half a world away. Description: M.SC.ICT MICROELECTRONICS&MICROSYSTEMS Tue, 01 Jan 2019 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/55233 2019-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/54107 Title: High efficiency low voltage class D CMOS audio power amplifier Abstract: Most modern devices and utilities that incorporate some form of audio input and audio, require and audio driver in order to create some sort of tune for the application-user. These audio drivers come in a variety of configurations and topologies, however the most widely used and commonly found in many applications are the Class-D Audio Power Amplifiers (CDA) due to the advantageous effects that they offer when compared to other types of consumer related audio amplifiers. this project shall comprise of both the design and implementation of a CDA using a CMOS 0.18 𝜇𝑚 process parameter and shall be modelled using the Cadence Virtuoso modelling suite. A Pulse-Width Modulation (PWM) CDA will be taken into consideration, deconstructed and each sub-component will be analysed in order to maximise the total efficiency of the end model. Hence, throughout this report, various modelling and implementation techniques shall be discussed, and stating why one approach was taken when compared to another. Description: B.SC.(HONS)COMPUTER ENG. Tue, 01 Jan 2019 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/54107 2019-01-01T00:00:00Z https://www.um.edu.mt/library/oar/handle/123456789/54106 Title: Implementation of a Sudoku puzzle solver on a FPGA Abstract: Sudoku is often considered as a casual puzzle game, which is played as a pastime. From a scientific perspective, the Sudoku puzzle features certain characteristics that entail finding a non-trivial solution, while giving the opportunity to explore and investigate several possibilities for solver implementations. Althoughatfacevalue, solving Sudoku puzzles seems to beaself-contained problem, in reality it encompasses a lot of properties which are useful to many other domains. In this work, the design, implementation and evaluation of a hybrid Sudoku puzzle solver on a Field-Programmable Gate Array(FPGA) is presented. The proposed Sudoku puzzle solver follows the specifications of the competition of the 2009 International Conference on Field-Programmable Technology (FPT). The solver initially makes use of simple pen-and-paper solving techniques to reduce the number of possible values and prune the overall search space. Once this is complete, the solver then utilises the brute-force search algorithm (also known as depth-first search algorithm) to systematically guess and back track through the puzzle, until a solution is reached. The implementation and testing of the Sudoku puzzle solver were carried out on a Xilinx Spartan-6XC6SLX45FPGA. Description: B.SC.(HONS)COMPUTER ENG. Tue, 01 Jan 2019 00:00:00 GMT https://www.um.edu.mt/library/oar/handle/123456789/54106 2019-01-01T00:00:00Z