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https://www.um.edu.mt/library/oar/handle/123456789/17817| Title: | Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter |
| Authors: | Casha, Owen Grech, Ivan Gatt, Edward Micallef, Joseph |
| Keywords: | Analog CMOS integrated circuits DC-to-DC converters Voltage-controlled oscillators Phase-locked loops |
| Issue Date: | 2010 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Casha, O., Grech, I., Gatt, E., & Micallef, J. (2010). Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens. 1196-1199. |
| Abstract: | This paper presents the measured results and characterisation of a 1.2 V CMOS low phase noise quadrature output phase locked loop (PLL) with an on-chip regulated DC-DC converter. In particular, it exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 38%. The automatic amplitude control loop in the VCO gives the facility to trade-off phase noise response with power consumption. In addition, this paper discusses important features of the DC-DC converter needed for reducing spurs in such applications. The results show the negligible effect of the on-chip DC-DC converter on the spur tone level of the PLL, provided a proper regulator scheme is used to limit the output voltage ripple. |
| URI: | https://www.um.edu.mt/library/oar//handle/123456789/17817 |
| Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| EXPERIMENTAL RESULTS OBTAINED FROM A 1.6 GHZ CMOS QUADRATURE OUTPUT PHASE LOCKED LOOP WITH ON-CHIP DC-DC CONVERTER.pdf Restricted Access | Experimental results obtained from a 1.6 GHz CMOS quadrature output phase locked loop with on-chip DC-DC converter | 1.35 MB | Adobe PDF | View/Open Request a copy |
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