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Results 1-10 of 17 (Search time: 0.014 seconds).
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Issue DateTitleAuthor(s)
2012An FPGA embedded system architecture for handwritten symbol recognitionBouvett, Emmanuel; Casha, Owen; Grech, Ivan; Cutajar, Michelle; Gatt, Edward; Micallef, Joseph
2011Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGAGambin, Isabel; Grech, Ivan; Casha, Owen; Gatt, Edward; Micallef, Joseph
2017An analytical model of the delay generator for the triggering of particle detectors at CERN LHCGauci, Jordan Lee; Gatt, Edward; De Cataldo, Giacinto; Casha, Owen; Grech, Ivan
2006Artificial neural network optimization for FPGABonnici, Mark; Gatt, Edward; Micallef, Joseph; Grech, Ivan
2017Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithmBuhagiar, Karl; Casha, Owen; Grech, Ivan; Gatt, Edward; Micallef, Joseph
2018A new FPGA-based controller card for the optimisation of the front-end readout electronics of charged-particle veto detector at ALICESeguna, Clive; Gatt, Edward; Gauci, Jordan Lee; De Cataldo, Giacinto; Grech, Ivan; Casha, Owen
2017Proposal for a new ALICE CPV-HMPID front-end electronics topologySeguna, Clive; Gatt, Edward; De Cataldo, Giacinto; Casha, Owen; Grech, Ivan
2017HLTB design for high-speed multi-FPGA pipelinesMagri, Josef; Casha, Owen; Bugeja, Keith; Grech, Ivan; Gatt, Edward
2018A new front-end readout electronics for the ALICE charged-particle veto detectorSeguna, Clive; Gatt, Edward; Grech, Ivan; Casha, Owen; De Cataldo, Giacinto
2011Verification of a VHDL GPS baseband processor using a simulink-based test bench generatorZarb, Terence; Grech, Ivan; Gatt, Edward; Casha, Owen; Micallef, Joseph