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Issue Date	Title	Author(s)
2012	An FPGA embedded system architecture for handwritten symbol recognition	Bouvett, Emmanuel; Casha, Owen; Grech, Ivan; Cutajar, Michelle; Gatt, Edward; Micallef, Joseph
2011	Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGA	Gambin, Isabel; Grech, Ivan; Casha, Owen; Gatt, Edward; Micallef, Joseph
2017	An analytical model of the delay generator for the triggering of particle detectors at CERN LHC	Gauci, Jordan Lee; Gatt, Edward; De Cataldo, Giacinto; Casha, Owen; Grech, Ivan
2006	Artificial neural network optimization for FPGA	Bonnici, Mark; Gatt, Edward; Micallef, Joseph; Grech, Ivan
2017	Hardware implementation of efficient path reconstruction for the Smith-Waterman algorithm	Buhagiar, Karl; Casha, Owen; Grech, Ivan; Gatt, Edward; Micallef, Joseph
2018	A new FPGA-based controller card for the optimisation of the front-end readout electronics of charged-particle veto detector at ALICE	Seguna, Clive; Gatt, Edward; Gauci, Jordan Lee; De Cataldo, Giacinto; Grech, Ivan; Casha, Owen
2017	Proposal for a new ALICE CPV-HMPID front-end electronics topology	Seguna, Clive; Gatt, Edward; De Cataldo, Giacinto; Casha, Owen; Grech, Ivan
2017	HLTB design for high-speed multi-FPGA pipelines	Magri, Josef; Casha, Owen; Bugeja, Keith; Grech, Ivan; Gatt, Edward
2018	A new front-end readout electronics for the ALICE charged-particle veto detector	Seguna, Clive; Gatt, Edward; Grech, Ivan; Casha, Owen; De Cataldo, Giacinto
2011	Verification of a VHDL GPS baseband processor using a simulink-based test bench generator	Zarb, Terence; Grech, Ivan; Gatt, Edward; Casha, Owen; Micallef, Joseph