Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/24013| Title: | Formal reasoning with Verilog HDL |
| Authors: | Pace, Gordon J. He, Jifeng |
| Keywords: | Computer hardware description languages Object-oriented methods (Computer science) Computer programs -- Verification |
| Issue Date: | 1998 |
| Publisher: | University of Malta. Faculty of ICT |
| Citation: | Pace, G. J., & He, J. (1998). Formal reasoning with Verilog HDL. Workshop on Formal Techniques for Hardware and Hardware-like Systems, Marstrand. 1-15. |
| Abstract: | Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are dened, and properties about synchronization and mutual exclusion algorithms are proved. |
| URI: | https://www.um.edu.mt/library/oar//handle/123456789/24013 |
| Appears in Collections: | Scholarly Works - FacICTCS |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| download (5).pdf | 209.73 kB | Adobe PDF | View/Open |
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