An analytical model of the delay generator for the triggering of particle detectors at CERN LHC

Abstract

This paper presents an analytical model of a tapped shift-register based delay generator, which is currently implemented in the High Momentum Particle Identification Detector (HMPID) at CERN and will be upgraded in the coming years. This work aims to verify whether this delay generator can be optimized to provide a delay range of 525 ns with a resolution of 1 ns. In particular, this paper studies how the clock jitter affects the delay generated and its linearity and predict how the current architecture will perform at a higher frequency of operation. The conclusions drawn via the analytical model, are then verified using both a simulation model and an FPGA implementation of the delay generator.