A new front-end readout electronics for the ALICE charged-particle veto detector

Abstract

The A Large Ion Collider Experiment (ALICE) upgrade strategy is based on collecting more than 10 nb-1 of Pb-Pb collisions at luminosities of 6x1027 cm-2s-1 which corresponds to a collision rate of 50 kHz for Pb-Pb and 200 kHz for pp and p-Pb. Such high beam luminosity requirements cannot be met with the presently existing electronics having a low readout rate of 5 kHz. This work presents the design of a new front-end readout electronics for the Charged-Particle Veto detector (CPV) module located in PHOton Spectrometer (PHOS). The proposed new architecture, when compared to prior systems, allows the parallel readout and processing of all 480 silicon photomultiplier pads that are connected to digital signal processing cards. Preliminary results demonstrate that this work will enable the CPV detector to reach an interaction rate of at least 50 kHz. The system design consists of three modules, each containing two segment boards, two Readout Common Boards (RCBs) and 16 digital signal processors called DiLogic cards. This paper presents the architecture layout and preliminary performance measurement results for the proposed new design. This work concludes with recommendations for other future planned updates in hardware schema.