Study-Unit Description

Study-Unit Description


CODE ESE2104

 
TITLE Sequential Logic Circuits

 
UM LEVEL 02 - Years 2, 3 in Modular Undergraduate Course

 
ECTS CREDITS 5

 
DEPARTMENT Electronic Systems Engineering

 
DESCRIPTION 1) Latches and Flip Flops:
RS, JK, D and T latches. Functional diagrams and truth tables and timing diagrams. Gated latches. Edge triggered flip flops: RS, JK, D, T. Master-slave flip flops.

2) Sequential Circuit Design:
Fundamental concepts of sequential circuits. State tables and state diagrams. Moore and Mealy state machines. Design and analysis using latches and flip flops. Propagation delay considerations on sequential circuit design and operation. Glitches and their impact on correct circuit operation. Handling glitches. Synchronous and asynchronous circuit operation considerations.

3) Multivibrators:
The monostable, astable and bistable multivibrators. Discrete transistor circuits and the 555 IC. Digital oscillators (clock circuits) using logic gates, including crystal oscillators.

4) Digital function building blocks:
Counters: Asynchronous and synchronous operation. Up/Down and cascaded counters. Counter applications and timers.
Shift Registers: Serial and parallel shift registers. Bi-directional shift registers. Shift register counters and applications.

Study-unit Aims:

This unit continues to build the student's knowledge in digital electronics, addressing sequential functional design and circuit implementation; timer and counter circuits.

Learning Outcomes:

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to:
- understand latch and flip flop logic and use,
- Design and analyse sequential circuits,
- Implement and use counter, timer, shift register, multivibrator and clock circuits,
- Trouble-shoot designs.

2. Skills:

By the end of the study-unit the student will be able to design, build and trouble-shoot sequential logic digital electronic circuits.

Main Text/s and any supplementary readings:
(Available in Library)

Floyd, Thomas L., Digital Fundamentals. Prentice Hall. ISBN: 0-13-085268-6.

 
ADDITIONAL NOTES Pre-requisite Study-unit: ESE1203

Please note that a pass in the Examination component is obligatory for an overall pass mark to be awarded.

 
STUDY-UNIT TYPE Lectures, Practical and Tutorials

 
METHOD OF ASSESSMENT
Assessment Component/s Assessment Due Sept. Asst Session Weighting
Practical SEM1 No 20%
Examination [See Add. Notes] (2 Hours) SEM1 Yes 80%

 
LECTURER/S David Zammit Mangion

 

 
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It should be noted that all the information in the description above applies to study-units available during the academic year 2023/4. It may be subject to change in subsequent years.

https://www.um.edu.mt/course/studyunit