Study-Unit Description

Study-Unit Description


CODE ESE3103

 
TITLE Introduction to FPGAs

 
LEVEL 03 - Years 2, 3, 4 in Modular Undergraduate Course

 
ECTS CREDITS 5

 
DEPARTMENT Electronic Systems Engineering

 
DESCRIPTION This study-unit introduces the student to the systematic design of advanced digital systems using FPGA's.

• Review of digital systems and use of FPGA's within modern products.
• Review of Logic arrays : Combinational and sequential circuit design using logic arrays. Timing diagrams.
• FPGA Architecture : Basic routing networks, Look Up Tables, IO Blocks, and cell architectures.
• VHDL: constructs, hierarchical design, structural/behavioral programming paradigms, digital system modelling, synthesis to hardware.
• Digital Design practices. Moore and Mealy Finite state Machines. Design for hardware accelerated processing.
• FPGA application design: Introduction to CAD tools for FPGA design flow, schematic entry, basic floor planning and timing.
• Basic interfacing of FPGAs with external devices. Design and construction of an application.

Laboratory work
• Hands-on VHDL practical sessions.
• Programming of an FPGA board with in-built peripheral application.

Study-Unit Aims:

This unit introduces the student to the planning, design and implementation of high performance digital system applications using VHDL.

This includes a methodical approach towards synthesis, simulation and verification of digital designs, as well as their interface with other electronic modules.

Tuition builds upon previous work, introducing the systematic application of Finite State Machines with Data Paths, as well as Algorithmic State Machine Charts.

A practical assignment serves as a consolidation of the material covered in the lectures.

Learning Outcomes:

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to:
• Determine the suitability of an FPGA within a modern digital system application.
• Distinguish between different PLD (eg FPGA) and ASIC technologies for implementing high performance logic circuits, highlighting the pros and cons for each.
• Describe the complete design flow from problem specification to working circuit.

2. Skills:

By the end of the study-unit the student will be able to:
• Plan, design, implement and test digital systems though various workflows.
• Write and Debug VHDL code to model a variety of digital electronic systems.
• Suitably document digital circuits designed in VHDL and their performance.

Main Text/s and any supplementary readings:

Main Texts:

• VHDL for Designers, Stefan Sjoholm and Lennart Lindh
• The Designers Guide to VHDL, Peter J. Ashenden
• The Design Warrior's Guide to FPGAs: Devices, Tools and Flows, Clive Maxfield
• VHDL: analysis and modeling of digital systems, Zainalabedin Navabi 1993
• VHDL designer's reference, Jean-Michel Berge et al. 1992
• VHDL '92, Jean-Michel Berge et al., 1993
• Introduction to VHDL, R.D.M. Hunter & T.T. Johnson, 1996
• VHDL coding styles and methodologies, B. Cohen, 1999
• VHDL: from description to synthesis, S. Yalamanchili

Supplementary Readings:

• Various Xilinx datasheets and Application Notes form www.xilinx.com

 
ADDITIONAL NOTES Pre-requisite Study-unit: ESE2104

 
STUDY-UNIT TYPE Lecture, Practical and Project

 
METHOD OF ASSESSMENT
Assessment Component/s Assessment Due Resit Availability Weighting
Practical SEM1 No 15%
Project SEM1 Yes 85%

 
LECTURER/S Andre Micallef (Co-ord.)

 
The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the description above applies to study-units available during the academic year 2020/1. It may be subject to change in subsequent years.

https://www.um.edu.mt/course/studyunit