Study-Unit Description

Study-Unit Description


CODE ESE3203

 
TITLE Digital Design with FPGAs 1

 
LEVEL 03 - Years 2, 3, 4 in Modular Undergraduate Course

 
ECTS CREDITS 5

 
DEPARTMENT Electronic Systems Engineering

 
DESCRIPTION This study-unit builds upon the previous study-unit and guides the student toward advanced high performance digital designs.

• VHDL: advanced libraries, test-benches and simulation.
• System integration of Intellectual property (IP) Hard and Soft Cores. Development of custom IP blocks.
• Introduction to transciever technology and soft core microcontrollers.
• Introduction to I/O technolgies and communication protocols, both internal and external to the FPGA.
• Formal verification methods for digital hardware design.
• Hardware environment consideration, including IO planning. Design for power, timing, speed or cost.

Laboratory work
• Programming of an FPGA board with inbuilt peripheral application.
• Interfacing of FPGA board with external components designed by students.

Study-Unit Aims:

The objective of this study-unit is to give the student an advanced understanding of digital design on an FPGA including formal verification methods and post-synthesis simulation.

With a working knowledge in VHDL, the student is then guided through the the complex design of a holistic high performance commercial system. This is done through the integration of custom code and off the shelf IP blocks.

A practical assignment serves as a consolidation of the material covered in the lectures.

Learning Outcomes:

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to:
• Describe the advanced keywords and programming constructs in VHDL.
• Describe detailed characteristics of a number of specific FPGA and I/O technologies.
• Describe techniques for producing high perfromance, industry capable designs.
• Describe the role of formal verification in the domain of hardware design.

2. Skills:

By the end of the study-unit the student will be able to:
• Write VHDL code utilising libraries and IP cores to model a variety of digital electronic systems.
• Create automated test-benches to test and validate the functionality of the VHDL code.
• Meet stringent timing criteria, through careful FPGA floor-planning and pipelined design while interfacing to high speed memory or high speed I/O busses.

Main Text/s and any supplementary readings:

Main Texts:

• VHDL for Designers, Stefan Sjoholm and Lennart Lindh.
• The Designers Guide to VHDL, Peter J. Ashenden.
• The Design Warrior's Guide to FPGAs: Devices, Tools and Flows, Clive Maxfield.
• VHDL: analysis and modeling of digital systems, Zainalabedin Navabi 1993.
• VHDL designer's reference, Jean-Michel Berge et al. 1992.
• VHDL '92, Jean-Michel Berge et al., 1993.
• Introduction to VHDL, R.D.M. Hunter & T.T. Johnson, 1996.
• VHDL coding styles and methodologies, B. Cohen, 1999.
• VHDL: from description to synthesis, S. Yalamanchili.

Supplementary Readings:

• Various Xilinx datasheets and Application Notes form www.xilinx.com

 
ADDITIONAL NOTES Pre-requisite Study-unit: ESE3103

Please note that a pass in the Examination component is obligatory for an overall pass mark to be awarded.

 
STUDY-UNIT TYPE Lecture, Practical and Project

 
METHOD OF ASSESSMENT
Assessment Component/s Assessment Due Resit Availability Weighting
Practical SEM2 No 15%
Project SEM2 Yes 25%
Online Examination [See Add. Notes] (3 Hours) SEM2 Yes 60%

 
LECTURER/S Andre Micallef (Co-ord.)

 
The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the description above applies to study-units available during the academic year 2020/1. It may be subject to change in subsequent years.

https://www.um.edu.mt/course/studyunit