Study-Unit Description

Study-Unit Description



LEVEL 03 - Years 2, 3, 4 in Modular Undergraduate Course


DEPARTMENT Microelectronics and Nanoelectronics

DESCRIPTION The study-unit covers digital VLSI design building blocks including Logic implementation: Combinational logic, Random logic (inverter, NAND, NOR gates) and their implementation in CMOS technology with particular emphasis on transistor sizing and the use of stick diagrams.

The study-unit also covers structured combinational logic including transistor switch arrays, distributed gate arrays and programmable gate arrays.

The Design of asynchronous sequential circuits, including state diagrams and flow tables, internal state reduction, secondary state assignment are detailed together with associated problems and solutions including Synchronisers, metastability, communicating between asynchronous clock domains, arbitrers, degrees of synchrony.

Finally procedures for Testing and optimal design for testability including Fault matrix, path sensitization, line justification, critical path generation are explained together with associated problems in testing and industrial test methods such as Scan path testing, built-in-self-test, BILBOs, and the use of controllability analysis.

Study-unit Aims

The study-unit aims at introducing the principles of digital logic design in integrated circuits, including random logic and structured logic implementation of combinational logic circuits. The students will acquire the relevant knowledge which will allow them to design and implement digital logic integrated circuits together with exposure to CAD tools required for the design of integrated circuits at semi-custom and full-custom level.

Learning Outcomes

1. Knowledge & Understanding:

By the end of the study-unit the student will be able to study digital logic design as employed in integrated circuits and familiarise with testing structures for digital IC.

2. Skills:

By the end of the study-unit the student will be able to design digital logic design in integrated circuits, will get familiar with CAD tools required for the design of integrated circuits at semi-custom and full-custom level and design testing structures for digital IC.

Main Text/s and any supplementary readings
(Availability at the Library or otherwise is indicated against each entry)


• Geiger R., Allen P., Strader N., VLSI Design Techniques for Analog and Digital Circuits. McGraw-Hill, ISBN 0-07-100728-8, 1990. (Available)

Reading List

• Fabricius E., Introduction to VLSI Design, McGraw-Hill, ISBN 0-07-100727-X, 1990. (Available)

• Lewis D. & Prothese D., Design of Logic Systems, Chapman & Hall, ISBN 0-412-42890-3, 1992. (Available)

• Pucknell D. & Eshraghian K., Basic VLSI Design, 3rd edition. Prentice Hall. ISBN 0-13-079153-9, 1995.

STUDY-UNIT TYPE Lecture, Practicum & Tutorial

Assessment Component/s Assessment Due Resit Availability Weighting
Practical SEM2 No 25%
Examination (3 Hours) SEM2 Yes 75%

LECTURER/S Ivan Grech (Co-ord.)
Nicholas Joseph Sammut

The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints.
Units not attracting a sufficient number of registrations may be withdrawn without notice.
It should be noted that all the information in the description above applies to study-units available during the academic year 2020/1. It may be subject to change in subsequent years.