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Title: The analysis of warpage in wafer-level compression molding
Authors: Farrugia, Russell
Grech, Ivan
Casha, Owen
Gatt, Edward
Micallef, Joseph
Ellul, Ivan
Duca, Roseanne
Borg, Ingram
Keywords: Finite element method
Three-dimensional integrated circuits
Electronic apparatus and appliances -- Plastic embedment
Integrated circuits -- Wafer-scale integration
Issue Date: 2015
Publisher: Springer Berlin Heidelberg
Citation: Farrugia, R., Grech, I., Casha, O., Gatt, E., Micallef, J., Ellul, I., ... Borg, I. (2015). The analysis of warpage in wafer-level compression molding. Microsystem Technologies, 21(12), 1-10.
Abstract: Advanced 3D MEMS packaging technologies involving the encapsulation of devices at wafer-level are being developed in order to achieve further minimization and cost reduction of consumer electronic devices. Com- pression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation. Excessive out-of-plane deformation has been reported in wafer-level compression molding trials using blank wafers which would negatively impact device reliability and the implementation of successive processes to the molded wafer. This paper presents finite element models of the molded wafer, with and without embedded dies which simulate the observed multi-state warpage characteristics. Molded wafer warpage measurements were also carried out in order to verify the applicability of the small and large deformation theories for layered plates and to verify the finite element model of the molded blank wafer. Possible factors (non-planar mold layer thickness and anisotropic wafer elastic properties) leading to asymmetric warpage in molded blank wafers were also investigated. From the molded wafer model with embedded dies the effects of flip-chip die dimensions and wafer thickness on the out-of- plane deformation together with possible reliability issues were analyzed.
Description: The work presented in this paper is part of the research undertaken by the authors in Lab4MEMS, which is an ENIAC Joint Undertaking financed project.
Appears in Collections:Scholarly Works - FacICTMN

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