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Title: Verifying hardware compilers
Authors: Pace, Gordon J.
Claessen, Koen
Keywords: Compilers (Computer programs)
Compiling (Electronic computers)
Computer hardware description languages
Sequential machine theory
Issue Date: 2005
Publisher: University of Malta. Faculty of ICT
Citation: Claessen, K. (2005). Verifying hardware compilers. 3rd Computer Science Annual Workshop (CSAW’05), Kalkara. 23-30.
Abstract: The use of hardware compilers to generate complex circuits from a high-level description is becoming more and more prevalent in a variety of application areas. However, this introduces further risks as the compilation process may introduce errors in otherwise correct high-level descriptions of circuits. In this paper, we present techniques to enable the automatic verification of hardware compilers through the use of finite-state model checkers. We illustrate the use of these techniques on a simple regular expression hardware compiler and discuss how these techniques can be further developed and used on more complex hardware- description languages.
Appears in Collections:Scholarly Works - FacICTCS

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