High frame rate image sensor pixel design

Abstract

This dissertation describes the study and design of pixel structures for image sensors tailored for high-speed imaging applications. Applications for such sensors range from commercial use to scientific research fuelling the need of this project. The different image sensor topologies are contrasted and evaluated in terms of operational speed, noise performance, size and cost. The pixel components in the image sensors are then studied in more detail focussing on the physical principles, structure and components used. The thorough analysis of such pixels includes a mathematical and circuit level model which is then simulated to verify their basic functionality and gain an appreciation of the advantages and disadvantages of different pixel types. The readout circuitry for these pixel topologies is another important aspect which allow an array of pixels to be read and accessed. The design of various types of readout circuits is done so that the image sensor chip may be interfaced correctly with off-chip external readout mechanisms such as oscilloscopes. The layout of such pixels is then carried out along with their associated readout circuitry so that an image sensor with different pixel structures can be manufactured for further testing and characterisation. In order to assess the layout process a parasitic simulation is also carried out to assess any differences in performance between the pre-layout circuit and the post-layout circuit. The final design gives an insight on what the future approach in designing ultra high speed image sensors should be. Future image sensors should aim to have parallel readout mechanisms such as the digital pixel sensor whilst maintaining a small size and low noise operation.