Modelling and simulation of a PLL-based transmitter for GSM

Abstract

Conventional transmitters for the global standard of mobile communication (GSM) use quadrature amplitude modulation (QAM) with in-phase (I) and quadrature (Q) base-band signals, mixed with carrier frequency signal from a local oscillator. This technique is complex, costly and power hungry due to the number of mixers and digital to analogue converters used to generate the I and Q signals. A more elegant GSM transmitter architecture utilises direct modulation of a high resolution sigma-delta frequency synthesizer and eliminates the need of I and Q base-band signals. The objective of this dissertation was to efficiently model such a transmitter architecture and facilitate the design and simulation prior to circuit implementation. A low cost Gaussian minimum shift keying (GMSK) technique is used, though this architecture is suitable for any continuous phase constant envelope modulation. The Gaussian filter was designed using an efficient look-up table implementation based on Feher’s filter. This implementation reduces the size requirement of the read-only memory by 50% with the use of control logic and encoder blocks. The proposed technique employs a phase-locked loop (PLL) based frequency synthesizer, used to control the phase and instantaneous frequency of the output signal. This design is suitable only for narrow-band modulation as the PLL closed-loop bandwidth is designed to be narrow in order to satisfy PLL noise requirements. The architecture is modelled using Simulink which helps in determining and optimising the hardware specifications necessary for this design.