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Title: An ASIC data readout processor for the ALICE HMPID and charged particle veto detectors
Authors: Seguna, Clive
Gatt, Edward
Grech, Ivan
Casha, Owen
De Cataldo, Giacinto
Keywords: Application-specific integrated circuits
Field programmable gate arrays
Position sensitive particle detectors
Issue Date: 2022
Publisher: Institute of Electrical and Electronics Engineers
Citation: Seguna, C., Gatt, E., Grech, I., Casha, O. & De Cataldo, G. (2022). An ASIC data readout processor for the ALICE HMPID and charged particle veto detectors. 2022 IEEE 21st Mediterranean Electrotechnical Conference (MELECON), Palermo.
Abstract: The A Large Ion Collider Experiment Charged Particle Veto detector is designed to suppress the detection of charged particles impinging on the front surface of the PHOton spectrometer detector, which consists of 17,920 lead tungsten crystal-based analogue detection channels. The Charged Particle Veto detector consists of three separate modules, each with an area of 200 x 230 cm2, placed on a PHOton spectrometer detector module. A typical event size for the Charged Particle Veto Detector consists of 1.3 Kbytes for Pb-Pb particles. The maximum event readout rate that the Charged Particle Veto detector can currently achieve is 10 kHz at 1% occupancy. Due to this technical limitation, a new electronic front-end readout system is currently being developed that can detect more than 10 nb-1 Pb-Pb collisions at a luminosity of up to 6 x 1027 cm-2s-1. In this work, we present the implementation of a new application-specific data readout integrated circuit for the charged particle veto detector fabricated in 180-nm semiconductor technology. This application specific integrated circuit-based processor can process 192 analogue channels simultaneously and improve the current readout rate by at least five times to 50 kHz. In addition, it includes an integrated zero-suppression technique, applies a triple modular redundancy strategy and a parallel cyclic redundancy check architecture for error detection and correction, and has four integrated 1 Gbps serializers for data transmission over low-voltage differential channels. The results of this development have shown that the use of this unique application specific integrated circuit-based processor in such front-end electronic readout detector systems results in at least 70 percent reduction in the use of costly components (e.g., field-programmable gate arrays, digital signal processors, clock circuits, decoupling components, etc.), a tenfold increase in readout rate, i.e., from 4 kHz to at least 50 kHz, and a reduction in power consumption from 5.2 mW to 0.625 mW per analogue channel compared to the current Charged Particle Veto detector front-end readout system. In addition, the developed application-specific 180 nm semiconductor architecture with 4 parallel readout circuits can be easily interfaced with other vendor-specific analogue-todigital converters currently available on the market, further facilitating the upgrade process of data acquisition systems.
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