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https://www.um.edu.mt/library/oar/handle/123456789/108840| Title: | A ±0.9V switched-capacitor CMOS multiplier with rail-to-rail input |
| Authors: | Grech, Ivan Micallef, Joseph Vladimirova, T. |
| Keywords: | Analog CMOS integrated circuits Linear integrated circuits -- Design and construction Electronic circuit design Analog-to-digital converters Radio circuits Mixed signal circuits Low voltage integrated circuits Modulators (Electronics) |
| Issue Date: | 1999 |
| Publisher: | The Institution of Electrical Engineers |
| Citation: | Grech, I., Micallef, J., & Vladimirova, T. (1999). ±0.9 V switched-capacitor CMOS multiplier with rail-to-rail input. Electronics Letters, 35(20), 1688-1689. |
| Abstract: | An analogue, fully differential, switched capacitor CMOS multiplier with rail-to-rail input capability is presented, together with simulation results. The multiplier can operate at a clock frequency of 10 MHz when operated from a ±0.9 V power supply. Special attention has been given to the minimisation of clock feedthrough errors and also to achieve a low common mode voltage error at the output. The latter makes the device suitable for use in correlators with large integration periods. |
| URI: | https://www.um.edu.mt/library/oar/handle/123456789/108840 |
| Appears in Collections: | Scholarly Works - FacICTMN |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A_±0.9_V_switched_capacitor_CMOS_multiplier_with_rail_to_rail_input.pdf Restricted Access | 229.12 kB | Adobe PDF | View/Open Request a copy |
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