Costas loop for BPSK carrier phase synchronisation implemented on an SDR hardware platform

Abstract

This paper presents the implementation of a custom hardware platform for software-defined radio, which was designed with increased functionality and product integration. The designed hardware consists of a Zynq-7000 SoC and an AD9361 RF front-end. Novel features in the hardware aspect of this design were added such as RF power amplification and switching. These were included to achieve an increased communication range and allow half-duplex transmission. Furthermore, a novel fast-locking Costas loop was implemented on the Zynq-7000 for carrier phase synchronization. The implementation was carried out using the Xilinx Model Composer in Simulink. This was applied to a binary phase shift keying wireless communication system for uncompressed real-time audio transmission, resulting in a maximum wireless data rate of 3.84 Mb/s.