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https://www.um.edu.mt/library/oar/handle/123456789/16601| Title: | A low-voltage CMOS multiplier for RF applications |
| Authors: | Debono, Carl James Maloberti, Franco Micallef, Joseph |
| Keywords: | Low voltage systems Analog CMOS integrated circuits Analog multipliers Radio frequency |
| Issue Date: | 2000 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Debono, C. J., Maloberti, F., & Micallef, J. (2000). A low-voltage CMOS multiplier for RF applications. International Symposium on Low Power Electronics and Design, Portacino Coast. 225-227. |
| Abstract: | A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 /spl mu/m CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB. |
| Description: | This work is part of a project funded under the Fourth Italian-Maltese Financial Protocol. |
| URI: | https://www.um.edu.mt/library/oar//handle/123456789/16601 |
| ISSN: | 15334678 |
| Appears in Collections: | Scholarly Works - FacICTCCE Scholarly Works - FacICTMN |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| OA Conference Paper - A low-voltage CMOS multiplier for RF applications (poster session).2-4.pdf | A low-voltage CMOS multiplier for RF applications | 244.85 kB | Adobe PDF | View/Open |
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