Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/24014| Title: | Correct hardware compilation with Verilog HDL |
| Authors: | Pace, Gordon J. |
| Keywords: | Computer hardware description languages Compilers (Computer programs) Compiling (Electronic computers) |
| Issue Date: | 1999 |
| Publisher: | Chalmers University of Technology |
| Citation: | Pace, G. J. (1999). Correct hardware compilation with Verilog HDL. Chalmers University of Technology. Gothenburg. |
| Abstract: | Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Duration Calculus, we give a number of algebraic laws which Verilog programs obey, using which, we then prove the correctness of a hardware compilation procedure. |
| URI: | https://www.um.edu.mt/library/oar//handle/123456789/24014 |
| Appears in Collections: | Scholarly Works - FacICTCS |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| download (6).pdf | 246.31 kB | Adobe PDF | View/Open |
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