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Title: Proposal for a new ALICE CPV-HMPID front-end electronics topology
Authors: Seguna, Clive
Gatt, Edward
De Cataldo, Giacinto
Casha, Owen
Grech, Ivan
Keywords: Field programmable gate arrays
Position sensitive particle detectors
Issue Date: 2017
Publisher: Institute of Electrical and Electronics Engineers
Citation: Clive, S., Gatt, E., De Cataldo, G., Casha, O., & Grech, I. (2017). Proposal for a new ALICE CPV-HMPID front-end electronics topology. 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos.
Abstract: This paper presents the proposal of a new front-end readout electronics (RO) architecture for the ALICE Charged-particle Veto detector (CPV) located in PHOton Spectrometer (PHOS), and for the High Momentum particle IDentification detector (HMPID). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the RO system shall achieve at least five times the speed of the present front-end readout electronics. Design choices such as using the ALTERA Cyclone V GX FPGA, the topology for parallel readout of Dilogic cards and an upgrade in FPGA design interfaces will enable the RO electronics to reach an approximate interaction rate of 50 kHz. This paper presents the new system hardware as well as the preliminary prototype measurement results. This paper concludes with recommendations for other future planned updates in hardware schema.
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