Design of a processor for embedded image processing applications

Abstract

The aim of this project is to design a microprocessor, or more generically, a processing element or system-on-chip that is optimised for real-time image processing tasks. This was primarily achieved through the design on an FPGA of various image-processing accelerating peripherals, each controlled by a softcore microcontroller. Thorough analysis of available literature including an extensive technical review resulted in the design to include hardware accelerators for morphology, convolution and RGB to HSV conversion. These peripherals were chosen due to their utility in image processing applications such as object recognition. A VGA peripheral was also designed so that the processor can display images. Processing for the morphology, convolution and VGA peripherals takes place independently of the processor’s routine since data is offloaded to the peripheral and the processor can then access the result when operation is complete. The design includes custom hardware, software together with available IPs by Xilinx Inc. The processor was also designed to be able to communicate with a PC interface that was designed in JAVA. This allows the user to transmit an image via ethernet and this is eventually stored in DDR4 memory accompanying the processor. Testing proved the capability of the system to successfully retrieve transmitted images. Processor was benchmarked with a modern Intel Core i7 CPU and whilst there are noticeable performance differences, the designed system’s power consumption is significantly lower by an order of magnitude of more than 10. Overall, the main aims of this project were achieved with a series of peripherals designed that can be integrated with a Xilinx Microblaze softcore processor in an FPGA. This resulted in an embedded processor that can execute the accelerated operations deterministically and in real-time. As can be seen in the results section all peripherals function as expected. Following testing, some limitations were identified particularly in the FPGA’s BRAM resources and in turn mitigation strategies such as the inclusion of a Direct Memory Access (DMA) module were suggested.