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https://www.um.edu.mt/library/oar/handle/123456789/77469| Title: | A high performance FPGA implementation for the front-end of vision-aided airborne navigation systems |
| Authors: | Borg, Nicholas Paul (2013) |
| Keywords: | Field programmable gate arrays GPS Integrated Navigation Systems Navigation equipment industry |
| Issue Date: | 2013 |
| Citation: | Borg, N. P. (2013). A high performance FPGA implementation for the front-end of vision-aided airborne navigation systems (Master’s dissertation). |
| Abstract: | With the availability and rapid advancement of low-cost, low-power and high-performance processors, machine vision is gaining popularity in the field of autonomous navigation. Imagery provides rich information about the surrounding environment that can be used to determine the position, velocity and attitude of a vehicle. However, real-time image processing is computational intensive. In this dissertation two hardware architectures were implemented on an FPGA with the objective to reduce the number of operation cycles and memory accesses of a vision-aided navigation system without degrading its accuracy. These implementations are targeted for micro- and small-sized Unmanned Aerial Systems (UAS) which have stricter limitations on cost, power consumption and payload size and weight. The first implementation adapts the SIFT feature detection and description algorithm to recognise underlying objects viewed from airborne platforms. The Gaussian filtering and Keypoint extraction stages of the SIFT algorithm were modified to drastically reduce the number of operation cycles and memory accesses, compared with the SIMD architecture. The number of memory accesses is reduced by 99.7% for 1920x1080 pixel images. The operation cycles of the Gaussian filtering stage is reduced by 90.2% using parallel systolic array architectures. An 87 .5% reduction in hardware resources is achieved by resizing the input images using altitude information available from onboard sensors and a Digital Elevation Model database. The Keypoint extraction stage was adapted from the HLSIFD algorithm since it generates more reliable features with fewer computations. The operation cycles of this stage is reduced by 95%. The second implementation is a hardware-based time-synchronisation circuit that synchronises raw measurements from the IMU, GPS and Camera with an accuracy of less than 1 millisecond. It also detects a GPS outage and switches between an IMU/GPS to an !MU/Camera system. |
| Description: | M.SC.ENG. |
| URI: | https://www.um.edu.mt/library/oar/handle/123456789/77469 |
| Appears in Collections: | Dissertations - FacEng - 1968-2014 Dissertations - FacEngESE - 2008-2015 |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| M.SC.ENG._Borg_Nicholas Paul_2013.pdf Restricted Access | 23.16 MB | Adobe PDF | View/Open Request a copy |
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