Please use this identifier to cite or link to this item:
https://www.um.edu.mt/library/oar/handle/123456789/87772| Title: | Supporting UML sequence diagrams using a processor net model |
| Authors: | Spiteri Staines, Tony |
| Keywords: | UML (Computer science) Petri nets |
| Issue Date: | 2007 |
| Publisher: | IEEE Computer Society |
| Citation: | Spiteri Staines, A. (2007). Supporting UML sequence diagrams using a processor net model. 14th Annual IEEE International Conference and Workshops on the Engineering of Computer-Based Systems (ECBS'07), Tucson. 279-286. |
| Abstract: | This paper describes how UML sequence diagrams can be supported using an executable processor net. Distributed real time transaction processing systems require validation, verification and performance analysis. A method for doing this is presented creating a processor net for a flight reservation. Some advantages of this approach are the creation of executable models, schemas, formalization and performance analysis. Other issues are discussed. |
| URI: | https://www.um.edu.mt/library/oar/handle/123456789/87772 |
| Appears in Collections: | Scholarly Works - FacICTCIS |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Supporting_UML_sequence_diagrams_using_a_processor_net_model.pdf Restricted Access | 520.15 kB | Adobe PDF | View/Open Request a copy |
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