A new FPGA-based controller card for the optimisation of the front-end readout electronics of charged-particle veto detector at ALICE

Abstract

The current Charged Particle Veto-detector (CPV) readout system of the ALICE (A Large Ion Collider Experiment) will be upgraded in 2018 for collecting more than 10 nb -1 of Pb-Pb collisions at luminosities of 6×10 27 cm -2 s -1 . The corresponding bandwidth of the detector must be increased by at least a factor of 10 from 4 kHz to a collision rate of 50 kHz for Pb-Pb particle collisions. The design of such a system is a challenging task, therefore various technologies and architecture topologies are being considered and investigated for the optimization of the front-end readout electronics. The upgrade proposed in this work has been tested and verified and preliminary results demonstrate that this work will enable CPV detector to reach interaction rate of at least 50 kHz or more. Optimization strategies include the use of a high-pin count 28 nm low-power FPGA technology for the simultaneous readout of digital signal processors called DiLogic cards, and use of high speed transceiver links at 3.125 Gbps. This paper presents the architecture layout and preliminary performance measurement results for this new design FPGA processor card. This work concludes with recommendations for other future planned updates in hardware schema.