Comprehensive VHDL Design: VLSI Digital Design for FPGA

Overview

This course provides a complete outlook into hardware description using VHDL. It begins by establishing the language's core syntax and semantics, emphasizing its main characteristics as a hardware programming language. It progresses to examining coding styles specifically for synthesis before moving on to Finite State Machine (FSM) design and reusable, parameterized components. The course will be taught in English, and each participant will receive a certificate of attendance upon completion.

Prerequisites

This course is suitable for both beginners in digital design and experienced designers who want to learn VHDL for FPGA development. Although extensive, the hands-on sessions are designed for participants with no prior knowledge of the Questa Verification Software. While some familiarity is recommended, it is not a requirement to join this course.

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Course Details

Start Date: 23-Mar-2026

End Date: 26-Mar-2026

Time: 9:00 to 12:00 & 13:00 to 16:00 each day (CET)

Location: Online Sessions

Closing Date: Registration closes 16-Mar-2026 or earlier if places are filled.

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Course Schedule

Day 1: VHDL Fundamentals & Hierarchy

• Introduction to VHDL: Uses of VHDL, the simulation cycle, and design flow.
• Design Units: Entity declarations and Architecture bodies.
• Design Hierarchy: Structural VHDL and component instantiation.
• Concurrent Statements: Signal assignments and data flow modelling.
• Basic Simulation: Setting up the simulator and viewing waveforms.
• Sequential Statements: The process block, sensitivity lists, and if/case statements.
• Signals vs. Variables: Understanding the difference in scheduling and hardware mapping.
• Data Types: std_logic, std_logic_vector, and standard libraries (IEEE 1164).
• Testbenches: Writing test harnesses, clock generation, and stimulus application.
• Response Checking: Using assert and report for self-checking verification.

Day 2: Synthesis, FSMs & Parametrization

• Coding for Synthesis: How VHDL constructs map to gates and flip-flops.
• Operators & Arithmetic: Using numeric std for signed/unsigned arithmetic.
• Finite State Machines (FSM): Mealy vs. Moore machines and safe coding styles.
• Parameterized Design: Using generics to create flexible, reusable modules.
• Advanced Data Types: Arrays, Records, and user-defined types.
• File I/O: Reading and writing files (TextIO) for complex testbenches.
• Memory Modelling: Inferring RAM and ROM structures.
• Subprograms: Using Functions and Procedures for cleaner code.

Day 3 and Day 4: Hands-On Software Tool Experience

The extensive practical hands-on sessions give delegates the chance to develop various VHDL code applications.

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Simulators:

• Siemens Questa

Reading List

• Roth Charles H., John Lizy Kurian, Digital Systems Design Using VHDL, Thomson, ISBN 978-0-495-24470-7
• Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 0-13-089161-4.

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The project is supported by the Chips Joint Undertaking and its members under grant agreement n.º 101217761.